For example, in the ISPSD (International Symposium on Power Semiconductor Devices & ICs) '05 pp. 367-370 (Non-Patent Document 1), T. Letavic et al. teach a structure in which, for the CMOS (Complementary Metal Oxide Semiconductor) process of 0.25 μm rule or below, an STI (Shallow Trench Isolation) region that is a trench device isolation region shallower than a generally used drift region for device isolation is arranged in a drift region of a power MOSFET.
In addition, in the ISPSD '05 pp. 339-342 (Non-Patent Document 2), C. Grelu et al. make a similar report.